Lalitha Immaneni

Lalitha Immaneni is a Vice President of Semiconductor Research & Development in the Assembly Test Technology Development organization for Intel Corporation. Lalitha manages a world class and diverse team of packaging architects, designers, and specialized engineers in the “Advanced Design & Customer Enabling” group, spanning multiple geographies (USA, Malaysia, and India). She leads the Back end technical interface to Intel’s foundry customers.

Lalitha is responsible for developing substrate/silicon, assembly, and board design rules, designing essential building blocks for emerging packaging technologies, developing electrical and physical design methodologies for packaging as well as delivering product package architectures, supporting product electrical analysis, and executing product designs for Intel Foundry. She is also responsible for the thermal, mechanical, and electrical analysis of Intel’s packaging choices and the implications across the product envelopes while also delivering industry leading power delivery and HSIO solutions.

Lalitha is a global leader and role model with a 30-year track record of stellar technical achievement in the semiconductor packaging industry. Her technical accomplishments include leading Intel through multiple transitions in the package design tools towards better efficiency and quality. Widely recognized within the packaging EDA partner community, Lalitha is known for driving design tool capabilities for die disaggregation. She has led many “firsts,” including enabling the definition of the first industry EDA packaging tool and leading package co-design for the first Foveros and EMIB products. She recently led the Package Assembly Design Kit delivery for Intel foundry Services and is currently focused on EDA ecosystem enablement, interoperable formats, and standards for chiplets.